Field of the Invention
The invention lies in the field of semiconductor technology and semiconductor manufacture.
Isolation trenches are frequently used in integrated circuits in order to insulate neighboring active zones or switching elements from one another. Such trenches, which are arranged in the semiconductor substrate and filled with an insulation material, may have different lateral and vertical dimensions depending on the boundary conditions given. Their surface generally terminates with that of the semiconductor substrate, this being achieved by means of a suitable planarization process. One problem with the use of such isolation trenches is that the trench etching causes crystal damage. Such crystal damage very often has negative consequences for the circuit to be fabricated, owing to the fact that, by way of example, the diffusion of impurity atoms is facilitated or the crystal structure of subsequently applied layers is deleteriously affected.
Although it is generally applicable, the problem underlying the invention is explained using a DRAM memory circuit with trench capacitors. In order to isolate neighboring memory cells, the so-called STI technique (Shallow Trench Isolation) is frequently employed. In the context of memory cells with trench capacitors, this is done, in particular, by means of an arrangement of the isolation trench which partly overlaps two capacitors in each case. In this case, first of all the capacitor trenches are fabricated and filled and then an isolation trench is etched in such a way that it partly covers the upper region of two neighboring trenches.
A conventional prior art method for fabricating the isolation trench is explained with reference to FIGS. 4 to 5. The capacitor trenches 2, 3 of mutually adjacent memory cells are completed in a semiconductor substrate 1. The trench wall is lined with a capacitor dielectric 4 in the lower region and with an insulation collar 5 made of silicon oxide, which is thicker by comparison with the dielectric liner 4, in the upper region. The insulation collar 5 can be removed in the vicinity of the upper edge of the trenches, in order to enable here the subsequent contact with the selection transistor of the cell. The capacitor trench is filled with polysilicon 6, which bears on the trench wall in the vicinity of the upper edge of the trenches. An isolation trench 7 is etched in such a way that the substrate located between the capacitor trenches 2, 3 and that part of the capacitor trenches which adjoins the substrate are covered. A mask for etching the isolation trench covers at least the active zone of the substrate. The trench, i.e., the STI trench, is etched down to a predetermined depth, in this case at least down to the insulation collar 5.
The etching of this STI trench causes damage in the substrate. The damage must be minimized, since the selection transistor of the memory cell is fabricated in the relevant substrate region following the capacitor trench. Annealing is effected by an oxidation process (furnace process or RTP), as a result of which a so-called "liner oxide" 8 is formed on the side wall and the bottom of the isolation trench 7. The liner oxide 8 additionally improves lattice matching during the filling of the isolation trench. The isolation trench is filled with an insulation layer 10.
During subsequent oxidation steps in the process (and to a small extent already during the oxidative annealing), however, structures located at a deeper level may also be oxidized, in particular the insulation collar 5 is oxidized further (see FIG. 2). As a result, there is the risk of crystal defects being formed in the substrate, which adversely affect the electrical properties of the memory cell (for example alternation of the retention time, so-called variable retention time) or lead to complete failure of the cell.
This problem has been countered heretofore by a thin nitride layer as an oxygen barrier on the liner oxide 8. The use of such a nitride layer is not without problems, however, since the lattice matching is not optimal and stresses may be produced. Furthermore, an additional furnace deposition is necessary.